| 摘要 |
PURPOSE:To increase an operation speed, to simplify the constitution of a circuit, and to increase integration density and storage capacity by connecting only storage cells in a selected row to bit lines by tri-state gates. CONSTITUTION:When a word line W1 for writing is selected and driven, only tri-state gates S1 and S2 directed from bit lines B1 and B2 to the side of ILLs (L1 and L2) generate two high and low logical outputs, and remaining tri-state gates S3 and S4 enter an electrically neutral high-impedance state. Consequently, only storage cells M in the selected row are connected to the bit lines B1 and B2 and write data Din from a data input buffer 3 is written; and storage cells in other unselected rows are disconnected from the bit lines B1 and B2 completely. Further, when a word line W2 for reading is selected and driven, only tri- state gates S3 and S4 directed from the IIs (L1 and L2) to the bit lines B1 and B2 generate two high and low logical outputs. |
