| 摘要 |
A fractional N synthesiser comprising a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the variable divider wherein the synthesiser is provided with first and second accumulators, the arrangement of the accumulators being such that an output signal from the arrangement is provided in which the interpolation sidebands of the first accumulator caused by quantisation errors in the first accumulator are cancelled, means being provided for setting the division ratio of the variable divider in dependence upon said output signal. |
