| 摘要 |
PURPOSE:To realize a high-speed synchronizing restoration circuit with a low- speed logical element by using a parallel processing circuit, providing a frame synchronizing circuit to apply frame synchronization to divided data in parallel and applying data processing in response to the synchronizing information. CONSTITUTION:Data 3, 4 are inputted to a frame synchronizing circuit 210 and DATA 5, 6 are inputted to a frame synchronizing circuit 211 respectively among data 3-6 divided into four by a serial converter 56. The frame synchronizing circuit 210 applies one bit instantaneous shift system to 2 parallel data and the frame synchronizing circuit 211 applies synchronization restoration. Since a frame bit exists in one data among the DATA 3-6, the synchronizing restoration is applied to any of the frame synchronizing circuits 210 and 211 and the other synchronizing circuit is in the hunting state. The synchronization restoring time is doubled but the number of the frame synchronization circuits is decreased. Thus, a low-speed and low-power consumption element is used in place of a high-speed and large-power consuming element. |
