| 摘要 |
PURPOSE:To reduce the power consumption of a complementary type device and highten the logic gate density as high as a single polarity device, by connecting a power cut-off switch to one of the two sets of inverters of an integrated circuit using a complementary MOS device. CONSTITUTION:When the multi-input logic circuit network 4 and N type MOS transistors (TR) QN9 and QN10 of an integrated circuit are not conducted, an FF circuit 1 holds ''1'' or ''0'' at a low power consumption. When a set signal S and input signals (a) and (b) are ''1'', the circuit network 4 and TRQN9 are conducted and a P type MOSTRQP9 is not conducted and, as a result, the circuit 1 is inverted and sets its output Q to ''0''. On the otherhand, when a reset signal (r) is ''1'', the TRQN10 is conducted and a circuit current is instantaneously made to flow through the conducted P type TR of the circuit 1. By setting the mutual conductance gm of the TRQN10 sufficiently large to the mutual conductance gm of the P type TR and holding the output after the circuit is inverted and the circuit current is cut off at ''0'', the power consumption of this integrated circuit is reduced. |
