| 摘要 |
PURPOSE:To omit a selecting circuit and a scan address terminal by positioning the 1st register group which is put in charge of control over the whole LSI on a scan path as the 1st stage, and selecting respective registers with a scan clock. CONSTITUTION:The 1st register group 4, the 2nd register group 5, and the 3rd register group 6 use different scan clocks. Namely, the 2nd and the 3rd register groups 5 and 6 set scan data with a scan clock SC4 and the 1st register group sets scan data with a scan clock SC3. Then, microinstruction registers, etc., are positioned as the 1st register group 4 as the 1st stage and one scan clock SC3 is applied to an input terminal for a scan mode 0 dedicated to the 1st register group 4. At this time, the 2nd register group 5 and the 3rd register group 6 generate no scan clock SC4, so data do not change. Thus, hardware and software are reduced. |
