发明名称 SEQUENCE FAULT DETECTOR FOR POLYPHASE CLOCK
摘要 PURPOSE:To improve the detecting accuracy of a sequence fault and also to use just a single detection system by detecting instantaneously the spot and dropout phenomena of an optional phase of a polyphase clock. CONSTITUTION:A discriminating means 20 confirms the signals allocated out of a clock sequence means 10 for each input of clocks Cj (j=1,...,n) of a single phase. then it is checked whether or not said confirmed signals are equal to those signals allocated to the clocks Cj of the corresponding phases, i.e., the signals given from output terminals k.n+j (k=0.1,...,i-1) of the means 10. If it is decided by the means that the signals allocated out of the means 10 to clocks Cj are not equal to those given from the terminal k.n+j, a sequence fault is detected with a polyphase clock.
申请公布号 JPS61193224(A) 申请公布日期 1986.08.27
申请号 JP19850031785 申请日期 1985.02.20
申请人 FUJITSU LTD 发明人 OHATA KIYOSHI
分类号 G06F1/04 主分类号 G06F1/04
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