| 摘要 |
PURPOSE:To simplify the circuit constitution by constituting the title demodulator with a counter measuring the period or half period of an FM signal, a storage device storing the counter output, a ROM having an output of the storage device as the address and a storage device storing the output of the ROM. CONSTITUTION:A zero cross detection output signal clears the counter 2 and a storage device 3 stores the count just before the counter is cleared. The stored value is given as the address of the ROM 4. A data corresponding to the address is written in addvance in the ROM 4. Thus, a demodulated output is obtained from the ROM 4 when the address is given. In order to eliminate the distortion in the demodulation output, storage devices 7a, 7b, 7c are provided and the zero cross detection output signal is frequency-divided by a frequency division circuit 10 to generate W1, W2, W3 as the write timing. Read signals R1, R2, R3 are formed by retarting the W1, W2, W3 at a counter 11 by Td and fed to an output enable terminal of tri-state buffers 8a, 8b, 8c. Then the data in the W1 is read by the R3.
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