| 摘要 |
<p>PHN. 10.511 14 In a charge transfer device in accordance with the invention, the channel (2) is subdivided at the area of the output into two subchannels (5, 6) provided with separate output gates (OG1, OG2) which are clocked in phase opposition and with separate reset gates (RG1, RG2) which are clocked likewise in phase opposition. Between the output gates and the reset gates there is arranged a floating gate (FG) common to both subchannels (5, 6), by which signals can be read during 100% of a clock period so that no additional filtering operations for filtering out spectra of higher order are required. This output circuit can be used in applications in which high speeds and a high sensitivity are required.</p> |
