| 摘要 |
PURPOSE:To shorten considerably a testing time by providing a check-bit switching circuit so that a memory cell-array functional test can be carried out in a lump every plural bits. CONSTITUTION:When an external controlling signal TE theoretical level is 'L', a normal read with ECC is performed. In the case of data-bit-test mode, in other words, when an external control signal TE theoretical level is 'H' and C/D theoretical level is 'L', a read-check-bit e which is generated from a data-bit c is compared with a write-check-bit-latch output m, and a data-bit- memory cell-array 3 can be tested. In the case of check-bit-test mode, in other words, when an external control signal TE theoretical level is 'H' and C/D theoretical level is 'H', a write-check-bit d and the write-check-bit-latch circuit output m are inputted to a syndrome generating circuit 6 and a check-bit- memory cell-array 4 can be tested.
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