发明名称 MULTIPROGRAMMABLE CONTROL DEVICE
摘要 PURPOSE:To rationalize the capacity of a memory by providing the memory of a data link device with an address conversion mechanism for addressing of this memory. CONSTITUTION:A programmable controller (PC) 210 is constituted with an essential PC consisting of CPU211, a main memory 211A, an I/O 212, and a common bus 213, a bus interface 214, and the data link device consisting of a connecting circuit 215 and a link data storage part 218. This link data storage part 218 is provided with a memory 216 for buffer and an address conversion mechanism 217. The address conversion mechanism 217 performs the address conversion for correspondence between addresses on a bus 219 and addresses of the main memory 216. In this address conversion, a block to which a given input/output address belongs is discriminated, and an address of the main memory 216 to which this block corresponds is calculated.
申请公布号 JPS61190603(A) 申请公布日期 1986.08.25
申请号 JP19850029436 申请日期 1985.02.19
申请人 HITACHI LTD 发明人 SASAKI WATARU;OKAMOTO TADASHI;YAMAOKA HIROMASA;SHIMOYAMA KAZUHIKO
分类号 G05B19/05 主分类号 G05B19/05
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