发明名称 METHOD OF ISOLATING MOS SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To suppress the intrusion of a channel stopper region into an active region, by selectively making a CVD oxide film to remain at the peripheral part of an oxidation resisting mask layer. CONSTITUTION:On a semiconductor substrate 1, a silicon oxide film 3 and an oxidation resisting mask layer 2 are formed. The layer 2 is etched, and a part, which is to become an isolating region 5, is exposed. The substrate 1 is etched, and the entire region 5 is recessed. Then, a CVD film 6 is deposited on the entire surface of the layer 2 and the region 5. Thereafter, reactive ion etching of the film 6 is performed, and only the part neighboring the layer 2 is made to remain. With the layer 2 and the film 6 as masks, ions are implanted, and an ion implanted layer 7 is formed in a range narrower than the region 5. The surface of the substrate 1 is oxidized by using the layer 2, and a thick field oxide film 8 is formed in the region 5. A channel stopper region 9 is formed beneath the film 8 at the same time.
申请公布号 JPS61191046(A) 申请公布日期 1986.08.25
申请号 JP19850031828 申请日期 1985.02.20
申请人 SANYO ELECTRIC CO LTD;TOKYO SANYO ELECTRIC CO LTD 发明人 OYABU HIROYUKI;AZUMA KOJI
分类号 H01L29/78;H01L21/76 主分类号 H01L29/78
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