发明名称 |
SOFTWARE SPECIFICATION VERIFICATION SYSTEM |
摘要 |
PURPOSE:To enable errors contained in the specification to be detected by making possible specification verification on the basis of optional error decision reference over specification element execution series. CONSTITUTION:In an error detection block detecting the presence or absence of specification errors, a block 31 executes transition or non-conditional transition on execution rules in a memory 2 as a function of specification elements in the register 5. When the processing of the operational processing is defined in the transition, the operation is executed. The block 32 actuates blocks 33 or 36 depending on whether the post-transition detection state is in the error detecting state or in the conditional error detecting state. After outputting the error detection information to the memory 8, the verification end flag is set by the block 33 which also actuates flag inspection blocks 17, 22. The block 34 checks the presence or absence of test conditions in the post-transition test state. The block 36 is the block for detecting and processing conditional error detection processing block for the post-transition detecting state. |
申请公布号 |
JPS61188640(A) |
申请公布日期 |
1986.08.22 |
申请号 |
JP19850028378 |
申请日期 |
1985.02.18 |
申请人 |
KOKUSAI DENSHIN DENWA CO LTD <KDD> |
发明人 |
WAKAHARA YASUSHI;NORIKOSHI MASAMITSU;TSUNODA YOSHIAKI |
分类号 |
G06F11/28;G06F9/06;G06F11/36 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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