| 摘要 |
PURPOSE:To improve the switching speed by using one of two sets of memory elements having equal cycle time as read and the other as write use and controlling them alternately. CONSTITUTION:A parallel PCM signal from a terminal IN is latched alternately by FFs 7, 8-11 and a talking data from the FF 8-11 is written sequentially to channel memories 1, 2 and channels 3, 4 alternately by using a command signal from an output control circuit 16 and a clock. Storage memories 5, 6 repeat read/write and the talking memories 1, 2 and the channel memories 3, 4 apply random read by using the output data of the storage memories 6, 5. FF 12, 13 and FF 14, 15 are latched respectively by CLK1, CLK0, an output control circuit 17 selects alternately one of the FF 12, 13 and FF 14, 15 to send the result to an output terminal OUT as a parallel PCM signal. |
