| 摘要 |
PURPOSE:To reduce the number of arithmetic steps of a high order polynomial by applying multiplication or division or addition at the same time, providing an auxiliary register to a high speed multiplication and division circuit and providing a selection circuit for an input from a data bus and an output of multiplication/division circuit to an input section of the adder circuit. CONSTITUTION:Registers (R) 1, 5, 6 store respectively input data. A conversion ROM 2 outputs a reciprocal of data of the R 1, an MPX 4 selects any of outputs of the R 1 and R 5 and of the ROM 2. A multiplication circuit 7 multiplies an output of the MPX 4 with an output of an R6 on a Galois field GF (2<m>). An MPX 8 selects either an input data or an output of the said operating device and a gate circuit 10 outputs the MPX 8 as it is or outputs 0. Further, an adder circuit 11 adds an output of the multiplication circuit 7 and an output of the circuit 10 on a Galois field GF (2<m>) and the result is used as the output of the said operating device. Thus, data S is stored in the R5, and gate control is applied at the same time to attain the operation obtaining S<k+1> from S<k> without inputting the data S. Further, the number of arithmetic steps is reduced by latching directly the result of operation to the R 9.
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