| 摘要 |
PURPOSE:To prevent pulse missing and double pulse in a count frame periodic signal output even when an external synchronizing signal having a timing jitter is used by inputting a count frame timing to a shift register having a length compensating a pre-decode quantity, using the output as a start signal and rewriting the said register in response to the external synchronizing signal. CONSTITUTION:A value from the count final value of a 1/N frequency division counter 1 by M-clock is decoded and an output is generated, an M-stage of shift register (SR) 4 inputting serially the output and loaded with a parallel input by an external synchronizing signal, and a means inputting '1' to one stage of the M-stage of the SR 4 and inputting '0' to the other stages are provided, the serial output of the SR 4 is used as the start signal of the counter 1 and this signal is used as a count frame period signal. Thus, when an external synchronizing signal exists in a range to the self-running frame timing, the said signal is used as a counter start signal with priority at all times.
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