| 摘要 |
PURPOSE:To prevent malfunction due to variance or the like of parts characteristics by providing a transparent latch on a data bus connecting a processor and a register to take sufficiently the data holding time for writing on the register. CONSTITUTION:A transparent latch 13 is provided on a data bus 5 connecting a processor 1 and a register 2, and a system clock pulse 8 is supplied to this latch 13. The data signal given to the data register 2 is fixed to the value at the time, when the clock pulse shown in a figure (a) is changed from the high level to the low level, as shown in a figure (c) and is not changed until the clock pulse is changed from the low level to the high level. Data is written surely because data to the register 2 is held even if the time when a write pulse, which is shown in a figure (d), for write on the data register 2 is changed from the low level to the high level is varied somewhat. |
