发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To distinguish a completely good produce from a defective product having a defect at an area whose error is correctable by including a means detecting the information bit inputted to an error correction circuit and presence in the error of check bit and outputting the result externally. CONSTITUTION:An output 16 of a parity check circuit 13 and information inputs D0-D7 are inputted to an error correction circuit 12, from which corrected information outputs A0-A7. Further, the output 16 of the parity check circuit 13 is inputted to a deciding circuit 14 comprising a NOR circuit to output an error detection output 15. If 1-bit error exists in the information inputs D0-D7 and the check inputs C8-C11, the syndrome of the output 16 goes to '0'. Even when the information outputs A0-A7 are not correct, if one-bit error exists in the inputs D0-D7, C8-C11, the output 15 goes to an L level. Thus, the completely good product and the defective product having a defect in error correctable area are distinguished from each other.
申请公布号 JPS61187199(A) 申请公布日期 1986.08.20
申请号 JP19850027074 申请日期 1985.02.14
申请人 NEC CORP 发明人 ADACHI TAKAO
分类号 G11C29/00;G11C29/42 主分类号 G11C29/00
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