| 摘要 |
PURPOSE:To write a data at every bit by providing an AND gate generating a bit write command signal, plural level detection circuits and an AND gate generating the write command signal for the entire storage circuit to the storage circuit. CONSTITUTION:The storage circuit consists of an address decode circuit 123, a storage cell 124, plural write data drive circuits 133-136, plural level detection circuits 125-128 and plural AND circuits 141-143. In such a case, the AND gate 141 generates a write command signal for the entire storage circuit. When the state of signal lines 103-106 is logical 0, corresponding write drive circuits 133-136 are inactivated and no data is written, but when the state of the signal lines 103-106 is logical 1, the corresponding write data drive circuits 133-136 are activated and the data is written in the storage cell 124 at a corresponding bit location.
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