发明名称 INSULATION GATE TYPE INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent surely multiplex selection by using a push-pull MOS inverter to the pre-stage of the output stage inverter of an address input signal drive circuit and using the push-pull inverter as the said output stage inverter. CONSTITUTION:The pre-stage of the output stage inverter of the address input signal drive circuit of an insulation gate integrated circuit is provided with push-pull inverters I3, -I3, I3', -I3' comprised of an enhancement drive MOS transistor (TR) and a load MOS TR having >=1 a mutual conductance gm ratio and the said output stage inverter consists of push-pull inverters I5, -I5 comprised of a load MOS TR having a depletion MOS TR and an enhancement MOS TR in parallel and of an enhancement drive MOS TR. In such a case, when the level of an address input signal is at a middle level, plural NOR circuit decoders are hardly in decoding at the same time, then the multiple selection of memory cells is prevented.
申请公布号 JPS61187192(A) 申请公布日期 1986.08.20
申请号 JP19850027745 申请日期 1985.02.15
申请人 TOSHIBA CORP 发明人 SUZUKI YOICHI;SEGAWA MAKOTO;ARIIZUMI SHOJI
分类号 G11C11/413;G11C11/34 主分类号 G11C11/413
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