| 摘要 |
PURPOSE:To reduce the amount of hardware required for bus right switching by outputting a hole request signal and a wait signal from a slave CPU to a master CPU. CONSTITUTION:When a master CPU1 outputs an operation start instruction to a slave CPU2, the slave CPU2 sets the wait signal and the hold request signal, which requests the bus right to the master CPU1, to the high level together. Hereafter, the slave CPU2 uses freely an address bus 4, a data bus 5, a memory 10, and an I/O 11 to execute programs After the execution of programs, the slave CPU2 sets the hold request signal and the wait signal to the low level together. The master CPU1 sets a hold acknowledge signal to the low level to take back the bus right. |
