| 摘要 |
PURPOSE:To improve the yield of write by providing the 2nd test memory cell provided corresponding to the 1st test memory cell and in nonwrite state so as to attain the test whether defective write is caused or not. CONSTITUTION:A word driver circuit WD6 is selected and connected, and a write current is applied from a bit line B3 of a dummy cell M36 to flow the current to the circuit WD6 via the cell M36. A diode D2 of the cell M36 is destructed and the write test with the same write current as the actual specification is connected to the bit line B3. In writing a signal to the cell M36, the dummy cell M35 is written and a dummy cell M45 is not written, a parasitic PNPN element is produced between the bit lines B3 and B4. The write current flows through the parasitic PNPN element and the same write current as that of the actual specification flows to the bit line B4 to conduct the write test and the current flows to the circuit WD6 selected by the word line W6 from the dummy cell M46 written by the test, and no write current flows to the desired dummy cell M36, then the write test as to whether or not any write defect is caused is conducted.
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