| 摘要 |
PURPOSE:To obtain plural timing signals by frequency-dividing variably a reference frequency, applying fixed frequency division further to the result and changing the frequency division of a variable frequency division circuit so as to output the timing signal applying n/m frequency-division to the reference frequency from the variable frequency division circuit. CONSTITUTION:A phase locked circuit is constituted of a loop circuit comprising a phase comparator 1, a low pass filter 2, a voltage controlled oscillator 3 and a 1/6 frequency division circuit 10, and a reference frequency f0 being 6 times the signal of an input signal f1 inputted to a phase comparator 1 is outputted from the voltage controlled oscillator 3 synchronously with the frequency f1. The reference frequency f0 is selected to a frequency being twice the frequency 2,304kHz being a least common multiple of, e.g., 14.4kHz and 768kHz. The output of the voltage controlled oscillator 3 is subject to 1/2 frequency division by a 1/2 frequency division circuit 6, the output is subject to frequency division by a 1/160 frequency-division circuit 9 and a timing signal f3 in 14.4kHz is obtained. Further, an output A of the voltage controlled oscillator 3 is subjected to 1/19 frequency division by the variable frequency division circuit 4, then a fixed frequency division circuit 5 applies 1/5 frequency division, and its output C controls the frequency division ratio of the variable frequency division circuit 4 to be 1/20 and a timing signal f1 in 240kHz is obtained.
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