发明名称 ERROR CORRECTION CODER
摘要 PURPOSE:To realize easily a coder making a specific code word effective by providing a selecting circuit selecting and outputting an information digit string while it is being inputted and selecting and outputting contents of a resister as a redundant digit string after the input of the information digit string is finished. CONSTITUTION:Both bit patterns X, Y are inhibited with information bit (0, 0), only a bit pattern X is inhibited with information bit (0, 1), only a bit pattern Y is inhibited with (1, 0) and a bit pattern from a read only memory 51 is given as it is in other cases. Each 4-bit bit pattern passing through gate circuits 52-1, 52-2 is subject to modulo 2 at each corresponding bit. The modulo 2 addition is subject to a modulo 2 addition combination circuit 53. Then a digit pattern converter 6 is constituted identically to a digit pattern converter in figure 2 and a data is fed from a register 7 to a redundant digit line in the unit of 2-bit. Through the constitution above, an error correction coder with code length of 12 and information bit of 8 can constitutes a coder with 2-bit parallel input/output.
申请公布号 JPS61184930(A) 申请公布日期 1986.08.18
申请号 JP19850024401 申请日期 1985.02.13
申请人 NEC CORP 发明人 NAKAMURA KATSUHIRO
分类号 H03M13/00 主分类号 H03M13/00
代理机构 代理人
主权项
地址