| 摘要 |
PURPOSE:To obtain a decoder circuit which consists of a small number of transistors TRs of the 1st conduction type and the TR of the 2nd conduction type whose gate connected between the 1st node and the 2nd power source is connected to one of gates of plural TRs of the 1st conduction type in common. CONSTITUTION:When input signals phi1-phi3 are '0', a P channel MOS TR Q1 is on and N channel MOS TRs Q2-Q4 are off, so a node N1 is precharged to a power source potential Vcc and an output node N4 is grounded. When the input signals phi1-phi3 are all '1', the P channel MOS TR Q1 turns on and all the N channel MOS TRs Q2-Q4 turn on. Therefore, the node N1 is grounded through the N channel MOS TRs Q2-Q4 and the output node N4 is held at the potential Vcc. Consequently, the decoder circuit operates without any precharge signal and by a small number of TRs.
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