| 摘要 |
PURPOSE:To improve the processing capacity and reliability of the whole of the system by controlling the corresponding terminal by a CPU only which can read up to the interruption classification, out of the CPU which receives the interruption starting from plural terminals. CONSTITUTION:When the first interruption occurs from an input output terminal 1-1, the interruption signal INT1 is inputted to interruption circuits 5-1-5-3, of CPU3-1-3-3. The CPU3-1, which completes earliest the instruction, is connected with an internal local bus 7-1 and a global bus 8, the bus 8 is occupied by the interruption access, interruption information A1 from an input output terminal 1-1 is read, interruption confirming information B1 is sent and the interruption processing of the terminal 1-1 is executed. At such a time, the CPU3-2, after the bus 8 is occupied, executes the usual internal processing after the spurious action timing. The CPU3-3 also occupies the bus 8 after the bus 8 is occupied, and executes the interruption processing of an input output terminal 1-2. When the second interruption of the terminal 1-1 occurs, the CPU3-2 occupies the bus 8, and the information A1 is read from the terminal 1-1 and the interruption processing is executed.
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