| 摘要 |
PURPOSE:To prevent logical processing amount from being increased even when the number of stages increased by including a transfer switching element connected in series with a transmission line and responding to a control signal, an integration capacitor, a charging switching element, a clock signal generating circuit and an operation circuit. CONSTITUTION:The transfer switching elements Q21, Q22, Q23, Q41, Qi1 are provided to a transmission line l1, the integration capacitors C2, C3, C4, Ci are connected to the transmission line at the post-stage of the elements and the switching mode of the charge switching elements Q22, Q32, Q42, Qi2 to charge the capacitors is changed at a prescribed period by using a low frequency clock signal phi2, the capacitor output is operated and given to the post-stage transfer switching elements. Thus, the product of outputs T1-Ti-1 of the 1st stage S1-(i-1)th stage is obtained at a connection point Ei1 in the i-th stage Si and an inverting circuit Ni1 produces the inverted product. Thus, the circuit constitution of the 2nd stage S2-i-th stage Si is identical and the circuit constitution is simplified. Further, a delay circuit A1 has a function taking a data when the clock signal phi3 or phi4 is at 'L' and holds the data when the phi1 or phi2 is at 'H'.
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