发明名称 BALANCED MODULATION CIRCUIT WITH CLAMP
摘要 PURPOSE:To prevent the carrier leakage of a balanced modulation circuit by providing a switch means to a clamp circuit, producing the same voltage drop as the forward voltage drop when a switching element is turned on so as to input a reference voltage to the balanced modulation circuit. CONSTITUTION:When a clamp pulse VCP given to a terminal 4 is at L level, a switching transistor (Tr) Q21 of the clamp circuit 1 is turned on and a current I3 flows to a resistor R1. In this case, a voltage difference between the reference voltage Vr of a reference voltage point 18 and a collector-emitter voltage VCE of the TrQ21 is converted by Trs Q26, Q6 and outputted at a terminal 6. A switch circuit 30 provided to the circuit 1 consists of a Tr Q30 having the equal characteristic as the Tr Q21 and resistors R31, R30 equal to resistors R1, R21 and one terminal of the resistor R31 is connected to a ground Vg, then a current I4 flowing to the resistor R31 is equal to a current I3, the voltage difference between the voltage Vr and the VCE of the TrQ30 is converted by Trs Q24, Q8, and an output voltage to the terminal 5 is equal to the voltage at the terminal 6. Thus, the supply voltage to the balanced modulation circuit 2 is equal and carrier leakage is prevented.
申请公布号 JPS61184077(A) 申请公布日期 1986.08.16
申请号 JP19850023076 申请日期 1985.02.08
申请人 OKI ELECTRIC IND CO LTD 发明人 KATASHIRO TAKASHI
分类号 H03C1/54;H03C1/60;H03G11/00;H04N9/65;H04N9/72 主分类号 H03C1/54
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