| 摘要 |
An interface circuit for use in a telephone communication system having at least one distributed processor controlling at least one port station circuit, said port station circuit and said interface circuit being in communication with a central processor over a common bus, said interface circuit characterized by means responsive to message requests on the bus for supplying information from said one distributed processor to said bus, means for monitoring said bus for signals identifying said one distributed processor and accepting central processor information from said bus, and means for establishing access to said bus by said port station circuit and by said interface such that said access is placed in a read-only mode when said distributed processor is malfunctioning or when said one port station accesses said bus during a bus access time reserved for said interface circuit. DEAB- DE3490263 C A group of control time slots of each system frame is reserved for the passage of control messages between a call processor and a control channel interface circuit. Each of the latter monitors the system bus and removes address information from the bus during time slot zero. - Microprocessor control information that is to be sent up-link to a call processor is stored in a control channel interface circuit output buffer. Upon being polled by a call processor, each control channel interface circuit of the group polled and having up-link information responds to the call processor by transmitting a one bit reply during the succeeding time slot two.
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