| 摘要 |
PURPOSE:To detect quickly a variation of a data by comparing new and old data by a harware, comparing its difference, generating an interruption if a variation occurs, and requesting a transfer suspension to a CPU. CONSTITUTION:When reading out a memory 1 by a CPU, a memory selecting signal inversion MS and a reading-out signal inversion RD become L, a bus buffer 4 makes a signal pass through to the right from the left, and the contents of the memory 1 are sent out onto data buses D0-D3. When executing write to the memory 1, a data sending-out signal DT/inversion R becomes H, and a signal ALE appaering in the beginning of a machine cycle becomes H. Therefore, an output signal SA of an AND gate 7 becomes H, and an output signal Qa of D-flip-flop 5a becomes H only at 1 clock time. In this way, the bus buffer 4 cuts the connection of the memory 1 and the data buses D0-D3. Also, read-out is requested to an inversion RD terminal of the memory 1 by an inversion output signal Qa of a D inversion flip-flop 5a. |
