| 摘要 |
PURPOSE:To quicken the leading time of a PLL modulator by decreasing the frequency division at power onto quicken the loop locking and switching the frequency division after phase locking is obtained. CONSTITUTION:At power on, a signal of an unlock alarm line 13 goes to logical 1, a changeover switch 12 connects to a phase comparator 3 and an output subjected to phase comparison in an FH connects to a low-pass filter 6. When phase locking is reached, the frequency of two signals FH given to the comparator 3 is equal. since the frequency divisions M, Q of frequency dividers 10, 11 are equal, the frequency of the two signals FL given to a phase comparator 9 reaches FH/Q. Then the level of the signal on the signal line 13 goes to logical 0, the switch 12 is thrown to the comparator 9 and the output subjected to phase comparison by the FL connects to the filter 6. Then phase locking is attained at the FL. Thus, the phase comparison frequency is switched from the FH to the FL to quicken the leading time.
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