| 摘要 |
PURPOSE:To reduce remarkably shift time of frequency division output of each stage, to reduce number of elements and to simplify wiring by providing a circuit inputting a frequency division input of a frequency divider of the pre- stage and the logical result of a frequency division output to the frequency division input of frequency dividers of multi-stage. CONSTITUTION:Frequency dividers D1-Dn and logical elements A2-An are provided and frequency division delay times d1-d3 of the frequency divider of each stage and arithmetic delay times a2-a3 of the logical elements are produced respectively. In this constitution, an input signal (n-1)i of a frequency divider Dn-1 of a pre-stage and its frequency division output signal (n-1)0 are ANDed by the n-th stage of logical element An and the result is used for an input ni of the frequency divider Dn of the n-th stage. The shift time of the frequency division output of the n-th stage is the sum of the accumulated opera tion delay time of the logical elements and the frequency division delay time of the frequency divider of the n-th stage.
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