| 摘要 |
PURPOSE:To operate comparatively stably the titled circuit to a biased data pattern by keeping accurately a discriminating level to discriminate '1', '0' of an input data. CONSTITUTION:A data integrated at each bit by a matched filter 11 enters an adder circuit 12, added with an output of a D/A converter 19 and the result is outputted to a zero cross detection circuit 13. When no DC offset exists in the PCM data input, an output of the zero cross detection circuit 13 is a changing point of N and (N+1) bits, while a DC offset exists, the output of zero cross detection is moved to the left/right. The output of the zero cross detection circuit 13 is inputted respectively to a timing extraction circuit 14, a transition detection circuit 15 and a lead/lag decision circuit 16 respectively. The detected data decision level is added to the PCM data by the adder circuit 12 to cancel the DC offset of the PCM data.
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