| 摘要 |
PURPOSE:To provide for a diversified operation by arranging so that signals of the data line of a memory array in which the column-system selecting circuit is formed as static circuit and the dynamic type memory cells are arranged in a matrix are taken by a latch circuit in accordance with predetermined timing signals. CONSTITUTION:A low-column decoder R,C-DCR receives inner complementary address signals formed by a low/column address buffer R,C-ADB to forma column switch select signal to execute addressing of the memory cell MC and a dummy cell DC. The column address buffer C-ADB is formed by a static type circuit and set into an operating state by address strobe signals. The column decoder C-DCR is similarly formed by a static type circuit and decodes address signals transmitted from the column address buffer C-ADB to perform selecting operation of the data line DL and an inversion DL by data line select timing signals.
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