| 摘要 |
PURPOSE:To reduce the effect of insufficient erasure at the time of after- recording by superposed writing by applying an interleave accompanying a block delay to an error detection code within the extent of a frame delay quantity between the data. CONSTITUTION:In a memory address producing circuit, a 41-frequency dividing counter 66 and a block number counter 62 drive a data read address for producing error correction code area C1 and ROMs 73, 74 for producing C1 address data write addresses. These two ROMs are added in an adder 75 to produce prescribed addresses 0, 3, 4,...38 and to read out the respective data and to produce 4 C1 codes P0-P3. Addresses 39-42 are also produced by the ROMs 73, 74 and the adder 62 to storage them in these positions. Data are read from the memory by using the count numbers 0-5,504 from a 5,504-frequency dividing counter 61 as addresses and recorded on a floppy disk. As a result, it is possible to apply an interleave accompanying block delay to the first or second error detection correction code within the extent of the frame delay amount between the data.
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