| 摘要 |
PURPOSE:To achieve a higher integration, by forming a MOS type FET employing the interface between a lower Si layer and a a first insulation layer as gate active interface and a CHEM FET employing an interface between an upper Si layer and a second insulation layer as gate active surface in a 3-D manner to be connected electrically therebetween. CONSTITUTION:N-type impurity dope regions 2 and 3 are formed on a p-type Si wafer 1 as the source and drain regions of a MOS type FET and then, a MOS type FET polysilicon gate 5 and a polysilicon wire 4 for electrical connec tion between the MOS type FET and a CHEM FET are formed in an SiO2 insulation layer 6. Subsequently, a p-type Si layer 7 is formed and after a laser annealing, n-type impurity dope regions 8 and 9 are formed on the polysilicon wire 4 to be the source and drain regions of the CHEM FET and finally, an insulation layer 10 for CHEM FET is formed. In such a manner, the CHEM FET and a CHEM FET output signal processing circuit MOS type FET are formed in a 3-D manner to have the chip area thereby improving the integration of an integrated chemical sensor. |
