| 摘要 |
PURPOSE:To prevent the deterioration in the using efficiency of an address conversion buffer by selecting a degeneration means optimum to the working characteristics of a program at a relevant time point by a selection means. CONSTITUTION:Multiplexers 312 and 313 are controlled by signals given from a division designating F/F310 for address conversion buffer TBL. Thus the high-order 20 bits of a virtual address on a virtual address register VAR301 are degenerated to low-order 4 bits of a segment number SN and the low-order 4 bits of a page number PN or to the low-order 2 bits of the SN and the low- order 6 bits of the PN (8 bits in all). This prevents the deterioration in the using efficiency of the buffer TBL.
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