| 摘要 |
PURPOSE:To eliminate problems as to parasitic element effect and to realize low consumptive electric power by a method wherein an element detached layer is provided to periphery of a C<2>MOS element, which constitutes <2>MOS circuit with high withstanding voltage formed on a semiconductor substrate. CONSTITUTION:Detached grooves 31-35 are formed on a semiconductor substrate 13 using anisotropy etching of RIE etc.. The detached grooves 31-35 are buried by dielectric etc. in postrior process. P-type diffused layers 16-19 are formed to detached region 51, 52, then a P-type MOS transistor is formed. P well layers 14, 15 are formed to detached region 53, 54, and N-type diffused layers 20-23 are formed in the P-type well layer, then an N-channel MOS transistor is formed. |
