Level detector.

摘要

For detecting whether an input signal is above or below a reference level in such a way that brief signal interruptions and negative spurious pulses are not interpreted as decreases below the reference level, the detector comprises an input comparator (1), a first delay circuit (5), a second delay circuit (10) and an output circuit. The first delay circuit (5) comprises a first integrator comprising a first transistor (T2) and a first capacitor (8), a first current source (7) and a second comparator (T3). The second delay circuit (10) comprises a second integrator comprising a second transistor (T4) and a second capacitor (13), a second current source (12) and a third comparator (Ts). The first delay circuit (5) and the second delay circuit (10) have equal delay times. In order to ensure that during detection of a decrease below the reference level a positive spurious pulse is not interpreted as an increase above the reference level a third Transistor (T6) connects a third current source (30) in parallel with the first current source (7) of the first delay circuit when the input signal lies below the reference level, so that the delay time of the first delay circuit (5) becomes smaller than that of the second delay circuit (10).