发明名称 CLOCK SYNCHRONIZATION SYSTEM
摘要 <p>A clock synchronization system in a digital data switching system, such as a digital PBX. The system has a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the local clock is synchronized with the second clock. The system is distributed by placing the local clock and the lowering frequency on the control module of the switching system and placing the comparator to one or more of the line card modules which is receiving the second clock signals. Communication between the comparator and lowering circuit may be over a single line.</p>
申请公布号 JPS61181298(A) 申请公布日期 1986.08.13
申请号 JP19850263633 申请日期 1985.11.21
申请人 DAVID SYSTEMS INC 发明人 JIYON EFU UEIKAARII
分类号 H04Q3/52;G06F1/04;H04J3/06;H04L7/00;H04L7/033;H04Q11/04 主分类号 H04Q3/52
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