Processing cell for fault tolerant arrays.

摘要

A processing cell (10) is provided for use in constructing fault tolerant arrays. It contains a processor (12) arranged to indicate a faulty or fault-free operational state. The cell (10) is arranged to receive input from any one of three western neighbours, and to provide output to any one of three eastern neighbours. It both generates and receives connection request and availability signals. Internal logic ensures its becoming connected as part of an operational (not necessarily straight) row of cells (64) in an array (62) if and only if the processor (12) is fault-free and it receives at least one pair of true request and availability signals from respective eastern and western neighbours. The internal cell logic (16 to 52) implements a priority scheme in which connection to a more northern neighbour to east or west is preferred to connection to one more southern. This avoids any mid-array connection hiatus. Further embodiments (250,300,320) of the invention provide for reconfigurable columns of cells in addition to the foregoing row reconfiguration.