| 摘要 |
PURPOSE:To attain plural main memory accesses with a less hardware quantities by converting the array element addresses to receive accesses in plural times and selecting one of plural conversion results every plural produced addresses. CONSTITUTION:A processing part 1 decodes an instruction stored in a memory 2 and calculates an operated address. Then the part 1 reads the operand data out of the memory 2 when necessary and carries out arithmetic processing to store this arithmetic result to the memory 2. Furthermore, the part 1 gives an access to the array data stored in the memory 2 and performs a vector operation. The array elements needed for operation are obtained by performing the address calculation from the head element address B and the inter-element distance D like B, B+D and B+2D and according to B+iXD (i=n-1, n: number of elements). An access control part 3 controls the access to be given to the memory 2 through the part 1 and also can process plural requests at a time through an interface 120.
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