发明名称 INSPECTION SYSTEM FOR LOGICAL CIRCUIT
摘要 PURPOSE:To evade in-phase transfer without increasing any system delay by adding a selecting mechanism which inputs system data or scan data during the transmission of a scan clock according to the mode to an output-side FF which is put in an in-phase state. CONSTITUTION:The system clock 2 and system data 3 are signals for normal operation control and scan data 4, the scan clock 5, and a scan address 6 are used only during inspection. A combinational circuit 10 consists of input FF groups 11-14 and output FF groups 15 and 16. When the system clock of an aimed FF is in phase with the system clock of the FF as its front stage, the selecting mechanism for the system data and scan data is provided so as to stored the system data without sending out the system clock to the aimed FF, thereby storing the system data by sending out the scan clock.
申请公布号 JPS61180156(A) 申请公布日期 1986.08.12
申请号 JP19850019940 申请日期 1985.02.06
申请人 HITACHI LTD 发明人 NISHIDA TAKAO;HIYAMA TORU;ISHIYAMA TAKASHI;MIYAMOTO SHUNSUKE
分类号 G01R31/28;G06F11/267 主分类号 G01R31/28
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