| 摘要 |
PURPOSE:To obtain high reliability with less number of check bits by limiting a device to a device read or written in a predetermined order in a channel and devising an error correction system suitable for the device. CONSTITUTION:(N-2) lines are used for information bits among N channels and the remaining 2 lines are used for check bits, and the error correction is applied by allocating the sum of modulo 2 of the information bits and the sum of modulo 2 of the information bits subject to one time slot dealy each to the (N-2) lines. When N is selected 4 for example, the 2-bit information is inputted in parallel with the input terminal of a storage device 1. The information is written immediately in channels 3, 3' and the check bit is produced through a coder 4 at the same time and written similarly in channels 3'' and 3'''. The the information is read in the same order as the write, an error is corrected through a decoder 5 and the result is outputted to a terminal 6. One bit in the inputted two information undergoes one time slot delay by a delay element 7 in a coder 4, the sum of modulo 2 with other 1-bit is applied by an adder circuit 8 and the result is written in the channel 3''.
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