| 摘要 |
A dynamic memory device has a plurality of column unit arrangements. Each of the column unit arrangements includes first and third bit lines connected through first and third switching transistors to a first input terminal of a sense amplifier and second and fourth bit lines connected through second and fourth switching transistors to a second input terminal of the sense amplifier. The other ends of the third and fourth bit lines are connected through fifth and sixth switching transistors to a corresponding data line. A switching control signal cuts off at least one of the first switching transistor group including the first and second switching transistors and the second transistor group including the third and fourth switching transistors during only a given period of time containing time points before and after a time point at which the fifth and sixth switching transistors are turned on when data is written into a memory cell selected from memory cells connected to the bit lines.
|
