Hierarchical diagnostic testing arrangement for a data processing system having operationally interdependent circuit boards

摘要

A diagnostic test facility for a processor having a plurality of boards hierarchically arranged with respect to processor function. The first and most independent board contains the processor microstore that stores the usual information plus the processor diagnostic subroutines required to test all boards. The processor is tested by executing the diagnostic subroutines associated with the first board and by collecting and comparing test data with predicted data as the subroutines are executed. The second board is tested by using the facilities on the first board and by executing diagnostic subroutines associated with the second board. In a similar manner the remaining hierarchically arranged boards are tested in sequence with the testing of each board using the circuitry on the priorly tested boards.