| 摘要 |
<p>A digital data processing system including a number of input/output units that communicate with a memory over an input/output bus and through an input/output interface. The input/output interface pipelines data transfers between the input/output units and the memory. The interface includes an incoming and outgoing buffer for queuing requests from the input/output units, and transfers from the memory. In the event of an error in the input/output interface's pipeline buffer, the interface transmits, by means of a fault cycle over the bus, information to the input/output unit that initiated the transfer unit to enable it to recover.</p> |
