| 摘要 |
<p>Protective circuitry for a monolithic ROM is shown to include six monolithic FETS interconnected so that two comprise a resistance-capacitance series circuit responsive to a biasing voltage applied thereto to produce a time-varying voltage and the remaining four monolithic FETS are interconnected to form a latching circuit having a "high" output when the time-varying voltage is below a predetermined level and a "low" output thereafter as long as the biasing voltage is applied.</p> |
