| 摘要 |
PURPOSE:To obtain a dRAM with stable operation by providing plural transistors for charging a Y-decoder node selecting a sense amplifier and charging from both sides of a parasitic resistor. CONSTITUTION:A transistor (MOST) 21 for charging the Y-decoder is provided and has its drain connected to a current source line Vcc and its source to a node N1, with charging signal clocks (precharging clocks) phi3 being received to its gate as input. In this manner, MOST's 14, 21 are provided for charging the Y-decoder selecting the sense amplifier and charging is made from both sides of the parasitic resistor 19, so that the nodes N1, N4 can be directly charged through MOST21. Thus, even when the rise of the Y-decoder output clock phi3 and the bounce in the positive direction of the substrate potential VBB compete with each other, charging of the node N1 is performed promptly as the node N2. Since the charging capability is now augmented, read/write on the bit line is facilitated while operational margin is also assured.
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