| 摘要 |
PURPOSE:To realize an interleaving system by using one RAM having memory capacity corresponding to one block by switching address assignment to a row and a column direction alternately, block by block, reading data with the front half of a specified RAM address and writing new data with the latter half, and varying the array of output data from the RAM. CONSTITUTION:An address counter 12 generates a RAM address for every block on the basis of a clock signal from a clock input terminal 2. An address selector 11 selects the row-directional assignment or column-directional assignment of the RAM address with the signal SEL from the address counter 12 and the RAM address from the address counter 12 is used for the address assignment of the RAM3. The data in the RAM address from the address selector 11 is read out of the RAM3 with the front half of the clock signal from -WE corresponding to the clock and new data inputted to the data input terminal 1 at this time is written the same RAM address with the latter half of the clock. The read data is inputted to a timing circuit 13.
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