发明名称 ARITHMETIC DEVICE
摘要 PURPOSE:To simplify an interface means installed in a processor system by performing data transfer between the processor system and an arithmetic device independently of the arithmetic operation of the arithmetic device. CONSTITUTION:Data is transmitted forth and back between the processor system and arithmetic device through a register file 19, and the arithmetic circuit 20 consists of a multiplier, a shifter, an adder, etc. When the arithmetic device is put in operation, the processor system side holds a terminal 16 at a logical level '0' firstly to inhibit the contents of an operand bus 21 from being outputted to a terminal 15; and data to be processed is applied to the terminal 15, an address signal indicating which address of the register file 19 the data is written is applied to a terminal 15, and a write indication signal is applied to a terminal 13. A clock signal is supplied to a terminal 12 at any time and this signal is applied to AND circuits 25-30 while inputted to a control circuit 18. The AND circuits 26, 28, and 30 operates when the clock signal is at a logical level '1' and the AND circuits 25, 27, and 29 operate when the clock signal is at a logical level '0'.
申请公布号 JPS61177536(A) 申请公布日期 1986.08.09
申请号 JP19850019521 申请日期 1985.02.04
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 ITO YOSHITAKA;ISHINO FUMIAKI;FUKAMI KENNOSUKE;INOUE JUNJI
分类号 G06F7/00;G06F12/00 主分类号 G06F7/00
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